About

Hello! I'm Maia, and you are .... Nice to meet you.

I'm a fourth-year computer science and computer engineering undergraduate student at the University of Southern California. After graduation, I'll be joining Lockheed Martin's Space division as a software engineer. In my free time, I like to be with my friends and family, go to cafes, restaurants, museums and performances. I also enjoy baking, reading, hiking, rocketry, photography and piano. Stay tuned for updates on this page!

Maia

Projects

VerilogCUDAPython

Distributed MLP on FPGA & GPU ↗

Distributed neural network accelerator implementing MLP inference across two FPGA boards. Parallel CUDA implementation serves as a high-performance benchmark.

VerilogFPGAVGA

Flappy Bird on FPGA ↗

Flappy Bird written in Verilog and synthesized onto an FPGA with real-time FSM gameplay.

PythonMySQLLLM

Guardian v2: AI Entity Link Discovery ↗

RAG pipeline automating the discovery of hidden entity relationships using SentenceTransformers, cosine similarity, and a self-hosted LLM on an airgapped Linux system.

C++Socket APITCP/UDP

Multi-Server Parking System ↗

Distributed parking reservation system using UNIX sockets across a client and three backend servers.

PythonComputer VisionKotlinJavascriptFirebase

FireLoc ↗

Real-time wildfire crowdsensing system using monocular depth mapping and DEM triangulation on smartphones.

PythonTLA+Distributed Systems

Leader-Election Algorithm with Formal Verification ↗

Fault-tolerant asynchronous leader election protocol using Python's asyncio, with formal correctness proofs and TLA+ specification verified by TLC Model Checker.

PythonPyGameGenetic Algorithms

Autopoietic Automata ↗

Artificial life simulation visualizing self-replicating code emerging from random noise via genetic algorithms.

PythonJavascriptJavascriptRest/Fast APIs

Vibe.ai ↗

Audio-to-data visualizer transcribing speech via OpenAI API and analyzing sentiment with Google Cloud Language API.

SystemVerilogVitis HLS

32-bit Hash Core ↗

32-bit hash accelerator in C++ with Vitis HLS, synthesized to Verilog RTL and verified in ModelSim/FPGA.

PythonFlaskRaspberryPi

Smart Plant ↗

IoT plant watering system with Flask web UI and Raspberry Pi, using threading for background automation.

Contact

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